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authorSergeyDegtyar <sndegtyar@gmail.com>2019-08-27 18:28:05 +0300
committerSergeyDegtyar <sndegtyar@gmail.com>2019-08-27 18:28:05 +0300
commit980830f7b82f2a974f43580f61e917f99fbb4e7e (patch)
treeef4b9cfe86945794171527976315924faf99e157 /tests/ecp5/dpram.v
parent134d3fea909bae02f4f814e3d649658502b44b73 (diff)
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Revert "Add tests for ecp5 architecture."
This reverts commit 134d3fea909bae02f4f814e3d649658502b44b73.
Diffstat (limited to 'tests/ecp5/dpram.v')
-rw-r--r--tests/ecp5/dpram.v20
1 files changed, 0 insertions, 20 deletions
diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v
deleted file mode 100644
index 2e69d6b3b..000000000
--- a/tests/ecp5/dpram.v
+++ /dev/null
@@ -1,20 +0,0 @@
-module top (din, write_en, waddr, wclk, raddr, rclk, dout);
-parameter addr_width = 8;
-parameter data_width = 8;
-input [addr_width-1:0] waddr, raddr;
-input [data_width-1:0] din;
-input write_en, wclk, rclk;
-output [data_width-1:0] dout;
-reg [data_width-1:0] dout;
-reg [data_width-1:0] mem [(1<<addr_width)-1:0]
-/* synthesis syn_ramstyle = "no_rw_check" */ ;
-always @(posedge wclk) // Write memory.
-begin
-if (write_en)
-mem[waddr] <= din; // Using write address bus.
-end
-always @(posedge rclk) // Read memory.
-begin
-dout <= mem[raddr]; // Using read address bus.
-end
-endmodule