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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:31:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:31:59 -0700 |
| commit | bca3cf684367ac5cf33ac05506d9e604a325bd3f (patch) | |
| tree | b2b29b441c108984719d0b470ec34b779abec511 /tests/asicworld | |
| parent | f7c7003a193361285ba59d1315c1e7c26c4c52f1 (diff) | |
| parent | e194e65358058f3a039636d2603cc093f7b75e50 (diff) | |
| download | yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.tar.gz yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.tar.bz2 yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.zip | |
Merge branch 'master' into xaig
Diffstat (limited to 'tests/asicworld')
| -rw-r--r-- | tests/asicworld/xfirrtl | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl index c782a2bd6..08bf4ccd8 100644 --- a/tests/asicworld/xfirrtl +++ b/tests/asicworld/xfirrtl @@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v combinational loop code_hdl_models_dff_async_reset.v $adff code_hdl_models_tff_async_reset.v $adff code_hdl_models_uart.v $adff -code_specman_switch_fabric.v subfield assignment (bits() <= ...) code_tidbits_asyn_reset.v $adff code_tidbits_reg_seq_example.v $adff code_verilog_tutorial_always_example.v empty module |