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authorClifford Wolf <clifford@clifford.at>2019-01-27 09:17:02 +0100
committerClifford Wolf <clifford@clifford.at>2019-01-27 09:17:02 +0100
commit9666cca9ddba2e6d242006e80d66277b8b4df0fd (patch)
treea49ee1e10803ba30cb29582790ff699663e6e632 /tests/asicworld
parent42c47a83dab873290040367455c48f619d83e2a3 (diff)
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Remove asicworld tests for (unsupported) switch-level modelling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/asicworld')
-rw-r--r--tests/asicworld/code_hdl_models_misc1.v22
-rw-r--r--tests/asicworld/code_hdl_models_mux21_switch.v22
-rw-r--r--tests/asicworld/code_hdl_models_nand_switch.v14
-rw-r--r--tests/asicworld/code_hdl_models_t_gate_switch.v11
4 files changed, 0 insertions, 69 deletions
diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v
deleted file mode 100644
index e3d9d5d64..000000000
--- a/tests/asicworld/code_hdl_models_misc1.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module misc1 (a,b,c,d,y);
-input a, b,c,d;
-output y;
-
-wire net1,net2,net3;
-
-supply1 vdd;
-supply0 vss;
-
-// y = !((a+b+c).d)
-
-pmos p1 (vdd,net1,a);
-pmos p2 (net1,net2,b);
-pmos p3 (net2,y,c);
-pmos p4 (vdd,y,d);
-
-nmos n1 (vss,net3,a);
-nmos n2 (vss,net3,b);
-nmos n3 (vss,net3,c);
-nmos n4 (net3,y,d);
-
-endmodule
diff --git a/tests/asicworld/code_hdl_models_mux21_switch.v b/tests/asicworld/code_hdl_models_mux21_switch.v
deleted file mode 100644
index 519c07fc5..000000000
--- a/tests/asicworld/code_hdl_models_mux21_switch.v
+++ /dev/null
@@ -1,22 +0,0 @@
-//-----------------------------------------------------
-// Design Name : mux21_switch
-// File Name : mux21_switch.v
-// Function : 2:1 Mux using Switch Primitives
-// Coder : Deepak Kumar Tala
-//-----------------------------------------------------
-module mux21_switch (out, ctrl, in1, in2);
-
- output out;
- input ctrl, in1, in2;
- wire w;
-
- supply1 power;
- supply0 ground;
-
- pmos N1 (w, power, ctrl);
- nmos N2 (w, ground, ctrl);
-
- cmos C1 (out, in1, w, ctrl);
- cmos C2 (out, in2, ctrl, w);
-
-endmodule
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v
deleted file mode 100644
index 1ccdd3a7c..000000000
--- a/tests/asicworld/code_hdl_models_nand_switch.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module nand_switch(a,b,out);
-input a,b;
-output out;
-
-supply0 vss;
-supply1 vdd;
-wire net1;
-
-pmos p1 (vdd,out,a);
-pmos p2 (vdd,out,b);
-nmos n1 (vss,net1,a);
-nmos n2 (net1,out,b);
-
-endmodule \ No newline at end of file
diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v
deleted file mode 100644
index 5a7e0eaff..000000000
--- a/tests/asicworld/code_hdl_models_t_gate_switch.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule