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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-20 00:37:43 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-20 00:37:43 +0200 |
| commit | eafc4bd49f3ff1e6a9e934aae065de183ca3a90e (patch) | |
| tree | 745ecd24ccb8f634b295d084eba29c0178c7c7fd /tests/asicworld/code_verilog_tutorial_addbit.v | |
| parent | 148caecca30ec4e8ebd459993f28560438131cb8 (diff) | |
| download | yosys-eafc4bd49f3ff1e6a9e934aae065de183ca3a90e.tar.gz yosys-eafc4bd49f3ff1e6a9e934aae065de183ca3a90e.tar.bz2 yosys-eafc4bd49f3ff1e6a9e934aae065de183ca3a90e.zip | |
Improve "show" handling of 0/1/X/Z padding
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_addbit.v')
0 files changed, 0 insertions, 0 deletions