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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 23:05:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 23:05:59 -0700 |
| commit | 8f93999129bfcd957dbb312d804c01525af6d07e (patch) | |
| tree | 525e34213945bca19fde1e75321e7a2f46d10ad0 /tests/asicworld/code_verilog_tutorial_addbit.v | |
| parent | 4ef03e19a8eafc324d3442f0642abf858071fdd4 (diff) | |
| download | yosys-8f93999129bfcd957dbb312d804c01525af6d07e.tar.gz yosys-8f93999129bfcd957dbb312d804c01525af6d07e.tar.bz2 yosys-8f93999129bfcd957dbb312d804c01525af6d07e.zip | |
Revert "write_json to not write contents (cells/wires) of whiteboxes"
This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4.
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_addbit.v')
0 files changed, 0 insertions, 0 deletions