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author | Clifford Wolf <clifford@clifford.at> | 2019-01-27 09:17:29 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-01-27 09:17:29 +0100 |
commit | bf798a9020f1a8281f42f7f69d8d05d9e75114cb (patch) | |
tree | a49ee1e10803ba30cb29582790ff699663e6e632 /tests/asicworld/code_hdl_models_nand_switch.v | |
parent | c82aa49d9efa81c1e6c6e2d1a7507e3155d279e3 (diff) | |
parent | 9666cca9ddba2e6d242006e80d66277b8b4df0fd (diff) | |
download | yosys-bf798a9020f1a8281f42f7f69d8d05d9e75114cb.tar.gz yosys-bf798a9020f1a8281f42f7f69d8d05d9e75114cb.tar.bz2 yosys-bf798a9020f1a8281f42f7f69d8d05d9e75114cb.zip |
Merge branch 'whitequark-write_verilog_keyword'
Diffstat (limited to 'tests/asicworld/code_hdl_models_nand_switch.v')
-rw-r--r-- | tests/asicworld/code_hdl_models_nand_switch.v | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v deleted file mode 100644 index 1ccdd3a7c..000000000 --- a/tests/asicworld/code_hdl_models_nand_switch.v +++ /dev/null @@ -1,14 +0,0 @@ -module nand_switch(a,b,out); -input a,b; -output out; - -supply0 vss; -supply1 vdd; -wire net1; - -pmos p1 (vdd,out,a); -pmos p2 (vdd,out,b); -nmos n1 (vss,net1,a); -nmos n2 (net1,out,b); - -endmodule
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