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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-10-23 19:04:00 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-10-24 23:52:37 +0200 |
| commit | d3b6b7fe981c13f50b61d76603ba8c6686188966 (patch) | |
| tree | fd9879a85c06944522316958383d12bb768b32a7 /tests/arch/xilinx | |
| parent | 623526d17d36fe85ac1b34ddd1026be34c826b9e (diff) | |
| download | yosys-d3b6b7fe981c13f50b61d76603ba8c6686188966.tar.gz yosys-d3b6b7fe981c13f50b61d76603ba8c6686188966.tar.bz2 yosys-d3b6b7fe981c13f50b61d76603ba8c6686188966.zip | |
xilinx: Fix attributes_test.ys
This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.
The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/attributes_test.ys | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys index 7bdd94a63..58552d8fb 100644 --- a/tests/arch/xilinx/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -16,8 +16,7 @@ select -assert-count 8 t:RAM32X1D # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v -prep -setattr -mod -set ram_style "distributed" block_ram +setattr -set ram_style "distributed" block_ram/m:* synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 32 t:RAM128X1D @@ -25,8 +24,7 @@ select -assert-count 32 t:RAM128X1D # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v -prep -setattr -mod -set logic_block 1 block_ram +setattr -set logic_block 1 block_ram/m:* synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RAMB18E1 |