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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-19 09:47:36 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | a179d918ec4e5ed595e8f556b159ab39679d4e6c (patch) | |
| tree | 36b4b53ba70b7d274e6b9e2d162a1c7f579aa41e /tests/arch/xilinx | |
| parent | e79376d6cb34d5c569a95ba0717be214aeac0556 (diff) | |
| download | yosys-a179d918ec4e5ed595e8f556b159ab39679d4e6c.tar.gz yosys-a179d918ec4e5ed595e8f556b159ab39679d4e6c.tar.bz2 yosys-a179d918ec4e5ed595e8f556b159ab39679d4e6c.zip | |
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 70c05f2c0..fec4c6082 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -15,7 +15,10 @@ stat select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT* %% t:* %D +select -assert-count 1 t:LUT2 +select -assert-count 3 t:LUT5 +select -assert-count 1 t:LUT6 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D design -load orig @@ -28,5 +31,8 @@ cd fsm # Constrain all select calls below inside the top module stat select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE -# FIXME: One more register than above? -select -assert-none t:BUFG t:FDRE t:LUT* t:MUXF* %% t:* %D +select -assert-count 1 t:LUT1 +select -assert-count 3 t:LUT3 +select -assert-count 6 t:LUT4 +select -assert-count 6 t:MUXF5 +select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D |