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| author | Diego H <diego@symbioticeda.com> | 2019-12-12 13:50:36 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 13:50:36 -0600 |
| commit | 937ec1ee78e5470c148d8c39387c7a80711af8a7 (patch) | |
| tree | 37859963ab6aec9dbe2b75635cb8087130c19c29 /tests/arch/xilinx | |
| parent | ab6ac8327f28b2ba9530c81cdbb5091a1ef91032 (diff) | |
| download | yosys-937ec1ee78e5470c148d8c39387c7a80711af8a7.tar.gz yosys-937ec1ee78e5470c148d8c39387c7a80711af8a7.tar.bz2 yosys-937ec1ee78e5470c148d8c39387c7a80711af8a7.zip | |
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/memory_params.ys | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys new file mode 100644 index 000000000..f279a4a6e --- /dev/null +++ b/tests/arch/xilinx/memory_params.ys @@ -0,0 +1,45 @@ +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits and addr <= 36: -> RAMB36E1 +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + |