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author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 14:56:15 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 14:56:52 -0800 |
commit | 9ab1feeaf11adb6b675ac4034e246cb137d07db9 (patch) | |
tree | 522f6b0f71f16bea0144dfdbafd142e894fc2dce /tests/arch/xilinx/latches.ys | |
parent | 2666482282421bb54213ba01054111eadc401373 (diff) | |
download | yosys-9ab1feeaf11adb6b675ac4034e246cb137d07db9.tar.gz yosys-9ab1feeaf11adb6b675ac4034e246cb137d07db9.tar.bz2 yosys-9ab1feeaf11adb6b675ac4034e246cb137d07db9.zip |
abc9_map.v: fix Xilinx LUTRAM
Diffstat (limited to 'tests/arch/xilinx/latches.ys')
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