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| author | David Shah <dave@ds0.me> | 2020-10-01 11:15:54 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-10-15 08:52:15 +0100 |
| commit | 4d584d9319e87023f3aee9f9bc86a036f670478c (patch) | |
| tree | 6c80347ec72c1dc36f5d77f0ce5b204a910bbfb7 /tests/arch/nexus/lutram.ys | |
| parent | f9ed9786bf8743e96aafb42838cfef5e18e35f29 (diff) | |
| download | yosys-4d584d9319e87023f3aee9f9bc86a036f670478c.tar.gz yosys-4d584d9319e87023f3aee9f9bc86a036f670478c.tar.bz2 yosys-4d584d9319e87023f3aee9f9bc86a036f670478c.zip | |
synth_nexus: Initial implementation
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/arch/nexus/lutram.ys')
| -rw-r--r-- | tests/arch/nexus/lutram.ys | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/arch/nexus/lutram.ys b/tests/arch/nexus/lutram.ys new file mode 100644 index 000000000..cd645f717 --- /dev/null +++ b/tests/arch/nexus/lutram.ys @@ -0,0 +1,19 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/nexus/cells_sim.v synth_nexus +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +stat +select -assert-count 8 t:WIDEFN9 +select -assert-count 16 t:LUT4 +select -assert-count 8 t:DPR16X4 +select -assert-count 36 t:FD1P3IX +select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D |