diff options
| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-05 18:53:14 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 21:36:38 +0200 |
| commit | 0d4c2f0a65de2fccd767a56b9698be3d913fdd9f (patch) | |
| tree | 1a893fd344cc7be071d175c9183bb9d10ffa89a5 /tests/arch/intel_alm/logic.ys | |
| parent | b5f3b70cfeed9421e6d0daa3a1ef968b2b670bc2 (diff) | |
| download | yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.tar.gz yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.tar.bz2 yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.zip | |
intel_alm: add Cyclone 10 GX tests
Diffstat (limited to 'tests/arch/intel_alm/logic.ys')
| -rw-r--r-- | tests/arch/intel_alm/logic.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys index fad45db74..e8b26a524 100644 --- a/tests/arch/intel_alm/logic.ys +++ b/tests/arch/intel_alm/logic.ys @@ -9,3 +9,17 @@ select -assert-count 1 t:MISTRAL_NOT select -assert-count 6 t:MISTRAL_ALUT2 select -assert-count 2 t:MISTRAL_ALUT4 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D + + +design -reset +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_NOT +select -assert-count 6 t:MISTRAL_ALUT2 +select -assert-count 2 t:MISTRAL_ALUT4 +select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
\ No newline at end of file |