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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-11-11 15:41:33 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-11-11 15:41:33 +0100 |
| commit | 3e0ffe05a79d3196b3644cddf422edb927673b04 (patch) | |
| tree | b518fa47c9a27aa37da0deceb66313d769e14c7c /tests/arch/ice40 | |
| parent | 362f4f996d49cca4be240d5c96fba013dd56a8cb (diff) | |
| download | yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.tar.gz yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.tar.bz2 yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.zip | |
Fixed tests
Diffstat (limited to 'tests/arch/ice40')
| -rw-r--r-- | tests/arch/ice40/fsm.ys | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 5aacc6c73..223ba070e 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -2,12 +2,15 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check + +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module +select -assert-count 4 t:SB_DFF select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 15 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D |