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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
commit | c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch) | |
tree | 79cce7951390a0068beeab26be5d310222059c51 /tests/arch/ice40/adffs.ys | |
parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
download | yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.gz yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.bz2 yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.zip |
Moved all tests in arch sub directory
Diffstat (limited to 'tests/arch/ice40/adffs.ys')
-rw-r--r-- | tests/arch/ice40/adffs.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys new file mode 100644 index 000000000..548060b66 --- /dev/null +++ b/tests/arch/ice40/adffs.ys @@ -0,0 +1,11 @@ +read_verilog adffs.v +proc +flatten +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNS +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D |