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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-02 12:44:06 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-02 12:44:06 -0800 |
| commit | b454735bea6727f346fdbbc28f261b40d91c61ba (patch) | |
| tree | 6e82d90b00f0bf65ae340d97d2df4fd1558bb2b4 /tests/arch/gowin/counter.ys | |
| parent | 345e98f87105316da9797e01bdbdd3932269cfdf (diff) | |
| parent | ef6548203cca239a98b00ea652a92fe3e20f97d7 (diff) | |
| download | yosys-b454735bea6727f346fdbbc28f261b40d91c61ba.tar.gz yosys-b454735bea6727f346fdbbc28f261b40d91c61ba.tar.bz2 yosys-b454735bea6727f346fdbbc28f261b40d91c61ba.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/arch/gowin/counter.ys')
| -rw-r--r-- | tests/arch/gowin/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys index 920479d44..bdbc7ee24 100644 --- a/tests/arch/gowin/counter.ys +++ b/tests/arch/gowin/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |