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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-07 11:09:25 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-07 11:09:25 +0100 |
| commit | 49c9b63e0fc45d550afa089eff8fb92b6dce88b7 (patch) | |
| tree | e454190eb1728f7ac06e60219acbd35afd4a9628 /tests/arch/efinix | |
| parent | ecb0c68f0751b3bd97f8da94e7bd2258987d58e1 (diff) | |
| download | yosys-49c9b63e0fc45d550afa089eff8fb92b6dce88b7.tar.gz yosys-49c9b63e0fc45d550afa089eff8fb92b6dce88b7.tar.bz2 yosys-49c9b63e0fc45d550afa089eff8fb92b6dce88b7.zip | |
Fix for non-deterministic test
Diffstat (limited to 'tests/arch/efinix')
| -rw-r--r-- | tests/arch/efinix/mux.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index b46f641e1..91c110ae0 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -36,6 +36,6 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:EFX_LUT4 +select -assert-min 11 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D |