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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-28 10:39:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-28 10:39:03 -0800 |
| commit | b741954461ec403401730774e4197f836d8d209b (patch) | |
| tree | ada4dabc8e3326edeecf9c133589085fb5bdbdc4 /tests/arch/common/memory_attributes | |
| parent | 825b96fdcffedec02b4eaaa5f9c4aee5bfc6942a (diff) | |
| parent | 5bba9c3640971e25544f2053b31eb152c138c3af (diff) | |
| download | yosys-b741954461ec403401730774e4197f836d8d209b.tar.gz yosys-b741954461ec403401730774e4197f836d8d209b.tar.bz2 yosys-b741954461ec403401730774e4197f836d8d209b.zip | |
Merge pull request #1726 from YosysHQ/eddie/fix1710
ast: fixes #1710; do not generate RTLIL for unreachable ternary branch
Diffstat (limited to 'tests/arch/common/memory_attributes')
0 files changed, 0 insertions, 0 deletions