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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 14:29:44 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 14:29:44 +0200 |
| commit | e8ef3fcdfcacbc711a4722deee95f0707634bed0 (patch) | |
| tree | 971fae1a1b7d3204827759454fa55accdc9bc01f /tests/arch/common/memory.v | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| parent | 190b40341abd73ab5edf0e6740b6526e9575253b (diff) | |
| download | yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.tar.gz yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.tar.bz2 yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.zip | |
Merge pull request #1454 from YosysHQ/mmicko/common_tests
Share common tests
Diffstat (limited to 'tests/arch/common/memory.v')
| -rw-r--r-- | tests/arch/common/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/common/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |