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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-11 10:20:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 07:36:53 -0700 |
| commit | 88bddb37c91e8fe136e5c9cc2ade20fadccd1946 (patch) | |
| tree | d6a822ef14477b462f84ff675e7ffc890936839a /tests/aiger | |
| parent | d21a07c7b5ef57de5428e5f7913338af582146b5 (diff) | |
| download | yosys-88bddb37c91e8fe136e5c9cc2ade20fadccd1946.tar.gz yosys-88bddb37c91e8fe136e5c9cc2ade20fadccd1946.tar.bz2 yosys-88bddb37c91e8fe136e5c9cc2ade20fadccd1946.zip | |
verilog: handle empty generate statement by removing gen_stmt_or_null...
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
Diffstat (limited to 'tests/aiger')
0 files changed, 0 insertions, 0 deletions