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authorEddie Hung <eddie@fpgeh.com>2019-06-04 11:53:51 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-04 11:53:51 -0700
commitf0e93f33cf089a1c1924e569700792bf198b6810 (patch)
treeced79a25f70800dd211fd74ce1c1c429181d8bd9 /techlibs
parent6cf092641f3e39b466f1f36617a1474f9ae36901 (diff)
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Add (* abc_flop_q *) to brams_bb.v
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/xilinx/brams_bb.v16
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/xilinx/brams_bb.v b/techlibs/xilinx/brams_bb.v
index a682ba4a7..f540d299d 100644
--- a/techlibs/xilinx/brams_bb.v
+++ b/techlibs/xilinx/brams_bb.v
@@ -19,10 +19,10 @@ module RAMB18E1 (
input [1:0] WEA,
input [3:0] WEBWE,
- output [15:0] DOADO,
- output [15:0] DOBDO,
- output [1:0] DOPADOP,
- output [1:0] DOPBDOP
+ (* abc_flop_q *) output [15:0] DOADO,
+ (* abc_flop_q *) output [15:0] DOBDO,
+ (* abc_flop_q *) output [1:0] DOPADOP,
+ (* abc_flop_q *) output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -143,10 +143,10 @@ module RAMB36E1 (
input [3:0] WEA,
input [7:0] WEBWE,
- output [31:0] DOADO,
- output [31:0] DOBDO,
- output [3:0] DOPADOP,
- output [3:0] DOPBDOP
+ (* abc_flop_q *) output [31:0] DOADO,
+ (* abc_flop_q *) output [31:0] DOBDO,
+ (* abc_flop_q *) output [3:0] DOPADOP,
+ (* abc_flop_q *) output [3:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;