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| author | whitequark <whitequark@whitequark.org> | 2018-12-05 13:14:44 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-05 16:30:37 +0000 |
| commit | e6034840702effa2ff0c2eee0cca046b5c097e86 (patch) | |
| tree | 0ac8f9ca4957e0f09fb6835f03e3880755c68481 /techlibs | |
| parent | 59eea0183ffaa453f77c6d439a9df8c1087c0fe0 (diff) | |
| download | yosys-e6034840702effa2ff0c2eee0cca046b5c097e86.tar.gz yosys-e6034840702effa2ff0c2eee0cca046b5c097e86.tar.bz2 yosys-e6034840702effa2ff0c2eee0cca046b5c097e86.zip | |
opt_lut: always prefer to eliminate 1-LUTs.
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions