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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-16 14:21:18 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-16 14:21:18 +0200 |
| commit | b6345b111d994ff0de1bcd91379db1c289feb03b (patch) | |
| tree | dcbf52a23670b218cdb2a732445f2847b8d0d563 /techlibs | |
| parent | c9def5407cd59e8542201217c890bbe4c89fff5c (diff) | |
| parent | 1f52332b8d4621d6c5ab1447e82b6e2e53600e52 (diff) | |
| download | yosys-b6345b111d994ff0de1bcd91379db1c289feb03b.tar.gz yosys-b6345b111d994ff0de1bcd91379db1c289feb03b.tar.bz2 yosys-b6345b111d994ff0de1bcd91379db1c289feb03b.zip | |
Merge pull request #1013 from antmicro/parameter_attributes
Support for attributes on parameters and localparams for Verilog frontend
Diffstat (limited to 'techlibs')
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