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author | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:04:10 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:04:10 +0100 |
commit | b005eedf369bc60ce5f7cba9a0db4694f22a360f (patch) | |
tree | 1f8454d41443fbb2c3a4f7f2b72cee5fd2482723 /techlibs | |
parent | 27a918eadf11cfe6cfe0eead022c8ff3336a855e (diff) | |
download | yosys-b005eedf369bc60ce5f7cba9a0db4694f22a360f.tar.gz yosys-b005eedf369bc60ce5f7cba9a0db4694f22a360f.tar.bz2 yosys-b005eedf369bc60ce5f7cba9a0db4694f22a360f.zip |
Added $assume cell type
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/common/simlib.v | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index bc343c62d..abd2af521 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1163,7 +1163,24 @@ input A, EN; `ifndef SIMLIB_NOCHECKS always @* begin if (A !== 1'b1 && EN === 1'b1) begin - $display("Assertation failed!"); + $display("Assertation %m failed!"); + $stop; + end +end +`endif + +endmodule + +// -------------------------------------------------------- + +module \$assume (A, EN); + +input A, EN; + +`ifndef SIMLIB_NOCHECKS +always @* begin + if (A !== 1'b1 && EN === 1'b1) begin + $display("Assumption %m failed!"); $stop; end end |