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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 13:29:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 13:29:18 -0700 |
| commit | af59856ba1be1f7cde3154994334f45500af6c22 (patch) | |
| tree | 63ee305d8ddc997ecf726f9466fe979ad37ad8d7 /techlibs | |
| parent | 832216dab072cb4f1793aeda07604fb2eb32b399 (diff) | |
| download | yosys-af59856ba1be1f7cde3154994334f45500af6c22.tar.gz yosys-af59856ba1be1f7cde3154994334f45500af6c22.tar.bz2 yosys-af59856ba1be1f7cde3154994334f45500af6c22.zip | |
xilinx_dsp_cascade to also cascade AREG and BREG
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions