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| author | Clifford Wolf <clifford@clifford.at> | 2016-02-13 08:20:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-02-13 08:20:19 +0100 |
| commit | a75f94ec4ae411d98d9882e423e0ae02eda4bd37 (patch) | |
| tree | c853dbdcf0ec6eddb61570695f8d0cb1bb499bd1 /techlibs | |
| parent | 7bd329afa07ad97969afa69faba925634b03252d (diff) | |
| download | yosys-a75f94ec4ae411d98d9882e423e0ae02eda4bd37.tar.gz yosys-a75f94ec4ae411d98d9882e423e0ae02eda4bd37.tar.bz2 yosys-a75f94ec4ae411d98d9882e423e0ae02eda4bd37.zip | |
Run dffsr2dff in synth_xilinx
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6358a266b..21d1fb1ea 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -91,6 +91,7 @@ struct SynthXilinxPass : public Pass { log(" fine:\n"); log(" opt -fast -full\n"); log(" memory_map\n"); + log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); @@ -196,6 +197,7 @@ struct SynthXilinxPass : public Pass { { Pass::call(design, "opt -fast -full"); Pass::call(design, "memory_map"); + Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); |