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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-19 16:55:43 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-19 16:55:43 +0200 |
| commit | a6aeb3dbf03eb9f09f57ded48d13e72241589374 (patch) | |
| tree | 8538eb42ad2df9d8fd0f4f745022ddce9827a09d /techlibs | |
| parent | 21e38bed98d3d6bc4ae5833f6f609ac8f12d6361 (diff) | |
| download | yosys-a6aeb3dbf03eb9f09f57ded48d13e72241589374.tar.gz yosys-a6aeb3dbf03eb9f09f57ded48d13e72241589374.tar.bz2 yosys-a6aeb3dbf03eb9f09f57ded48d13e72241589374.zip | |
Added renaming of wires and cells to "rename" command
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions