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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-31 11:12:06 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-31 11:12:06 +0200 |
| commit | a3c16a05657e639a04d647a15af56b6fbce25e17 (patch) | |
| tree | 7f3abae5f718086367cc549d600b656040eaf0b7 /techlibs | |
| parent | 90b44113d89cd1f028e7805e0990dae43e2efa6f (diff) | |
| download | yosys-a3c16a05657e639a04d647a15af56b6fbce25e17.tar.gz yosys-a3c16a05657e639a04d647a15af56b6fbce25e17.tar.bz2 yosys-a3c16a05657e639a04d647a15af56b6fbce25e17.zip | |
Fix TRELLIS_FF simulation model
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 75a1aad1f..5bdb8395e 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter REGSET = "RESET"; parameter [127:0] LSRMODE = "LSR"; - reg muxce; - always @(*) + wire muxce; + generate case (CEMUX) - "1": muxce = 1'b1; - "0": muxce = 1'b0; - "INV": muxce = ~CE; - default: muxce = CE; + "1": assign muxce = 1'b1; + "0": assign muxce = 1'b0; + "INV": assign muxce = ~CE; + default: assign muxce = CE; endcase + endgenerate wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; |