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| author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-06-25 17:08:29 +0200 |
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| committer | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-06-25 17:08:29 +0200 |
| commit | a27fa1833e6dadf02645a12febb78853b5786151 (patch) | |
| tree | 5ca433fdba0e4968b5ac0dd1685d070c2bd9732f /techlibs | |
| parent | 4d4117c998db8f58a436ec9ea9c930bce85febef (diff) | |
| download | yosys-a27fa1833e6dadf02645a12febb78853b5786151.tar.gz yosys-a27fa1833e6dadf02645a12febb78853b5786151.tar.bz2 yosys-a27fa1833e6dadf02645a12febb78853b5786151.zip | |
added wrappers for Design, Modules, Cells and Wires
Diffstat (limited to 'techlibs')
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