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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 23:43:23 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 23:43:23 -0700 |
commit | 9b9bd4e19f3da363eb3c90ef27ace282716d2e06 (patch) | |
tree | ecac832b5971b8323058182d443db9dad9497c2f /techlibs | |
parent | 09b778744dc036d54209644884e9dc9138f95771 (diff) | |
download | yosys-9b9bd4e19f3da363eb3c90ef27ace282716d2e06.tar.gz yosys-9b9bd4e19f3da363eb3c90ef27ace282716d2e06.tar.bz2 yosys-9b9bd4e19f3da363eb3c90ef27ace282716d2e06.zip |
Move ff_map back after ABC for shregmap
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8ce552780..f45126dc5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -280,9 +280,7 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_cells")) { - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v "); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("clean"); } @@ -299,7 +297,9 @@ struct SynthXilinxPass : public ScriptPass // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); + run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } |