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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 10:23:03 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 10:23:03 +0100 |
| commit | 910556560fbf26df4f2960b7d94039a1f399f1a1 (patch) | |
| tree | 0275d15fa8aa833995f68784f205b2842a0ccb48 /techlibs | |
| parent | ef151b0b30c7b7253aceba6d184e7721a4eff0c0 (diff) | |
| download | yosys-910556560fbf26df4f2960b7d94039a1f399f1a1.tar.gz yosys-910556560fbf26df4f2960b7d94039a1f399f1a1.tar.bz2 yosys-910556560fbf26df4f2960b7d94039a1f399f1a1.zip | |
Added $meminit cell type
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index a73c6ee09..6707e190b 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1514,6 +1514,28 @@ endmodule // -------------------------------------------------------- +module \$meminit (ADDR, DATA); + +parameter MEMID = ""; +parameter ABITS = 8; +parameter WIDTH = 8; + +parameter PRIORITY = 0; + +input [ABITS-1:0] ADDR; +input [WIDTH-1:0] DATA; + +initial begin + if (MEMID != "") begin + $display("ERROR: Found non-simulatable instance of $meminit!"); + $finish; + end +end + +endmodule + +// -------------------------------------------------------- + module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter MEMID = ""; |