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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 13:54:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 13:54:40 -0700 |
| commit | 8f9d529929f43e6ba98f06159ae9533984c6264f (patch) | |
| tree | 7ef5827908abea33af3528e469e0e164ab26c59b /techlibs | |
| parent | 021f8e549266fb500d19f7a3b7747cad6eda22c2 (diff) | |
| download | yosys-8f9d529929f43e6ba98f06159ae9533984c6264f.tar.gz yosys-8f9d529929f43e6ba98f06159ae9533984c6264f.tar.bz2 yosys-8f9d529929f43e6ba98f06159ae9533984c6264f.zip | |
$pastQ should be first input
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 24512ecf7..5dc93e508 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -62,32 +62,32 @@ RAM128X1D 7 0 17 2 $__ABC_ASYNC 1000 0 2 1 0 764 -# Inputs: C CE D R \$pastQ +# Inputs: $pastQ C CE D R # Outputs: Q FDRE 1001 1 5 1 -- 109 -46 358 0 +0 - 0 0 0 -# Inputs: C CE D R \$pastQ +# Inputs: $pastQ C CE D R # Outputs: Q FDRE_1 1002 1 5 1 -- 109 -46 358 0 +0 - 109 -46 358 -# Inputs: C CE CLR D \$pastQ +# Inputs: $pastQ C CE CLR D # Outputs: Q FDCE 1003 1 5 1 -- 109 - -46 0 +0 - 109 - -46 -# Inputs: C CE CLR D \$pastQ +# Inputs: $pastQ C CE CLR D # Outputs: Q -FDCE_1004 1 1 5 1 -- 109 - -46 0 +FDCE_1 1004 1 5 1 +0 - 109 - -46 -# Inputs: C CE D PRE \$pastQ +# Inputs: $pastQ C CE D PRE # Outputs: Q FDPE 1005 1 5 1 -- 109 -46 - 0 +0 - 109 -46 - -# Inputs: C CE D PRE \$pastQ +# Inputs: $pastQ C CE D PRE # Outputs: Q FDPE_1 1006 1 5 1 -- 109 -46 - 0 +0 - 109 -46 - |