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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-15 13:00:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-15 13:00:00 +0100 |
| commit | 881dcd8af988664b92a85daa5d82e90b1df29b51 (patch) | |
| tree | 00a92d296a345e38a2d7387f992e14a6c90c39e2 /techlibs | |
| parent | 40f021e1367af8cc8cd2ea133ba4cb0d2f342cbd (diff) | |
| download | yosys-881dcd8af988664b92a85daa5d82e90b1df29b51.tar.gz yosys-881dcd8af988664b92a85daa5d82e90b1df29b51.tar.bz2 yosys-881dcd8af988664b92a85daa5d82e90b1df29b51.zip | |
Added final checks to "synth" and "synth_xilinx"
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/synth.cc | 21 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 10 |
2 files changed, 24 insertions, 7 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index a50db53ee..56ab6eaff 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -90,12 +90,14 @@ struct SynthPass : public Pass { log(" techmap\n"); log(" opt -fast\n"); #ifdef YOSYS_ENABLE_ABC - log("\n"); - log(" abc:\n"); log(" abc -fast\n"); log(" opt -fast\n"); #endif log("\n"); + log(" check:\n"); + log(" hierarchy -check\n"); + log(" check\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { @@ -172,15 +174,20 @@ struct SynthPass : public Pass { Pass::call(design, "opt -full"); Pass::call(design, "techmap"); Pass::call(design, "opt -fast"); + + if (!noabc) { + #ifdef YOSYS_ENABLE_ABC + Pass::call(design, "abc -fast"); + Pass::call(design, "opt -fast"); + #endif + } } - #ifdef YOSYS_ENABLE_ABC - if (check_label(active, run_from, run_to, "abc") && !noabc) + if (check_label(active, run_from, run_to, "check")) { - Pass::call(design, "abc -fast"); - Pass::call(design, "opt -fast"); + Pass::call(design, "hierarchy -check"); + Pass::call(design, "check"); } - #endif log_pop(); } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7812fa290..02207593a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -98,6 +98,10 @@ struct SynthXilinxPass : public Pass { log(" techmap -map +/xilinx/cells_map.v\n"); log(" clean\n"); log("\n"); + log(" check:\n"); + log(" hierarchy -check\n"); + log(" check -noinit\n"); + log("\n"); log(" edif:\n"); log(" write_edif synth.edif\n"); log("\n"); @@ -195,6 +199,12 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "clean"); } + if (check_label(active, run_from, run_to, "check")) + { + Pass::call(design, "hierarchy -check"); + Pass::call(design, "check -noinit"); + } + if (check_label(active, run_from, run_to, "edif")) { if (!edif_file.empty()) |