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author | William D. Jones <thor0505@comcast.net> | 2021-01-29 18:14:13 -0500 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
commit | 8348c45e4f679b44b238c0f205e2e3815c909c38 (patch) | |
tree | a711146a578afa58ace19f3e79b146b5f542d872 /techlibs | |
parent | 120404bfda90578a014ba702d457eb85ae3711d7 (diff) | |
download | yosys-8348c45e4f679b44b238c0f205e2e3815c909c38.tar.gz yosys-8348c45e4f679b44b238c0f205e2e3815c909c38.tar.bz2 yosys-8348c45e4f679b44b238c0f205e2e3815c909c38.zip |
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/machxo2/cells_map.v | 6 | ||||
-rw-r--r-- | techlibs/machxo2/cells_sim.v | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v index a02630703..15428d4dc 100644 --- a/techlibs/machxo2/cells_map.v +++ b/techlibs/machxo2/cells_map.v @@ -28,7 +28,7 @@ endmodule module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule // IO- "$__" cells for the iopadmap pass. -module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .EN(1'b1)); endmodule +module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b1)); endmodule module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule -module \$__FACADE_TOUTPAD (input I, OE, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .EN(OE)); endmodule -module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .EN(OE)); endmodule +module \$__FACADE_TOUTPAD (input I, OE, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(OE)); endmodule +module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(OE)); endmodule diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 3dd41334e..4e2a1bb6c 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -162,16 +162,16 @@ module FACADE_IO #( parameter DIR = "INPUT" ) ( inout PAD, - input I, EN, + input I, T, output O ); generate if (DIR == "INPUT") begin assign O = PAD; end else if (DIR == "OUTPUT") begin - assign PAD = EN ? I : 1'bz; + assign PAD = T ? I : 1'bz; end else if (DIR == "BIDIR") begin - assign PAD = EN ? I : 1'bz; + assign PAD = T ? I : 1'bz; assign O = PAD; end else begin ERROR_UNKNOWN_IO_MODE error(); |