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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 16:58:33 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-07 17:20:34 +0000 |
| commit | 7ff5a9db2d17c384260c2220c9205a7b4891f001 (patch) | |
| tree | b2a11d22feab846070dda3612ad60b0504ca8caa /techlibs | |
| parent | c38ea9ae65b2a987d6a7ea790abf339944069f9a (diff) | |
| download | yosys-7ff5a9db2d17c384260c2220c9205a7b4891f001.tar.gz yosys-7ff5a9db2d17c384260c2220c9205a7b4891f001.tar.bz2 yosys-7ff5a9db2d17c384260c2220c9205a7b4891f001.zip | |
equiv_opt: pass -D EQUIV when techmapping.
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index e0a07af32..c554c3f35 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -928,6 +928,7 @@ module SB_SPRAM256KA ( output reg [15:0] DATAOUT ); `ifndef BLACKBOX +`ifndef EQUIV reg [15:0] mem [0:16383]; wire off = SLEEP || !POWEROFF; integer i; @@ -954,6 +955,7 @@ module SB_SPRAM256KA ( end end `endif +`endif endmodule (* blackbox *) |