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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-04 10:48:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-04 10:48:42 +0200 |
| commit | 7a74ae4c5403ce68a8245c45359d49f80d6e863a (patch) | |
| tree | 466fe6d273608383eb0e275b9a942f9832770d16 /techlibs | |
| parent | 658f93663b12d3199f636cad8bf75aa1ee58108b (diff) | |
| parent | 12000b90de0bade5fca641c49f3375316220ed39 (diff) | |
| download | yosys-7a74ae4c5403ce68a8245c45359d49f80d6e863a.tar.gz yosys-7a74ae4c5403ce68a8245c45359d49f80d6e863a.tar.bz2 yosys-7a74ae4c5403ce68a8245c45359d49f80d6e863a.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 1152ffe63..b7dbe81a2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -153,6 +153,17 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); endmodule +module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT); + + parameter GAIN = 1; + parameter INPUT_MODE = "SINGLE"; + + initial VOUT = 0; + + //cannot simulate mixed signal IP + +endmodule + module GP_POR(output reg RST_DONE); parameter POR_TIME = 500; |