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| author | Adam Izraelevitz <azidar@gmail.com> | 2016-11-21 17:28:17 -0800 |
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| committer | Adam Izraelevitz <azidar@gmail.com> | 2017-02-13 11:17:53 -0800 |
| commit | 794cec00166f46a3ea8480377ee7f773884a8f5d (patch) | |
| tree | 6f106d56447804bcc14fc86a5e67ed6cdac5a88c /techlibs | |
| parent | 69468d5a16f87616af9c7f084f6ff247f3513050 (diff) | |
| download | yosys-794cec00166f46a3ea8480377ee7f773884a8f5d.tar.gz yosys-794cec00166f46a3ea8480377ee7f773884a8f5d.tar.bz2 yosys-794cec00166f46a3ea8480377ee7f773884a8f5d.zip | |
More progress on Firrtl backend.
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
Diffstat (limited to 'techlibs')
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