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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 18:15:49 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 18:15:49 -0700 |
| commit | 791114382774cdf70b16cc5f1cec689f0ddb5c0b (patch) | |
| tree | d065cfae037568e7b7e3da58871a07eecef9ea70 /techlibs | |
| parent | a048fc93e8cf187b28bd5ed924643671b9314678 (diff) | |
| download | yosys-791114382774cdf70b16cc5f1cec689f0ddb5c0b.tar.gz yosys-791114382774cdf70b16cc5f1cec689f0ddb5c0b.tar.bz2 yosys-791114382774cdf70b16cc5f1cec689f0ddb5c0b.zip | |
Create new $__XILINX_SHREG_ cell for variable length too
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions