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| author | Clifford Wolf <clifford@clifford.at> | 2017-11-23 08:48:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-11-23 08:51:38 +0100 |
| commit | 777f2881d880c7690c33821a90c990a8cebd275d (patch) | |
| tree | c0b06a2395d71403d670f6ae0ddbb3bf7e844a51 /techlibs | |
| parent | 5b6e52118c09bb5967efc2bc2ebe53b9608bad89 (diff) | |
| download | yosys-777f2881d880c7690c33821a90c990a8cebd275d.tar.gz yosys-777f2881d880c7690c33821a90c990a8cebd275d.tar.bz2 yosys-777f2881d880c7690c33821a90c990a8cebd275d.zip | |
Add Verilog "automatic" keyword (ignored in synthesis)
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions