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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-03-04 12:55:02 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-03-04 12:55:02 -0800 |
| commit | 6d2ea6fe5563205c0f565810d615c4900d4508d8 (patch) | |
| tree | e042d8e294ca9a7ea7d65b83142ebe86270e1153 /techlibs | |
| parent | 4cce7f6967313772207448569635e6e5c6bc44ce (diff) | |
| parent | 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 (diff) | |
| download | yosys-6d2ea6fe5563205c0f565810d615c4900d4508d8.tar.gz yosys-6d2ea6fe5563205c0f565810d615c4900d4508d8.tar.bz2 yosys-6d2ea6fe5563205c0f565810d615c4900d4508d8.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 8320ee70a..1e4002ee0 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; + wire srval; generate if (LSRMODE == "PRLD") - wire srval = M; + assign srval = M; else - localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0; + assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; endgenerate initial Q = srval; |