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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 16:06:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 16:06:13 -0700 |
| commit | 4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0 (patch) | |
| tree | 1a0ddae8fac57dfa8e39250895179974b687b0e9 /techlibs | |
| parent | aa0b107afbe800e040886829d43e0b9fcb7219c0 (diff) | |
| download | yosys-4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0.tar.gz yosys-4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0.tar.bz2 yosys-4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0.zip | |
Fix spacing
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/mux_map.v | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v index b7ff6ca90..4c1bb7d05 100644 --- a/techlibs/xilinx/mux_map.v +++ b/techlibs/xilinx/mux_map.v @@ -52,21 +52,21 @@ module \$shiftx (A, B, Y); else assign A_without_x[i] = A[i]; - if (B_SIGNED) begin - if (B_WIDTH < 4 || A_WIDTH <= 4) - wire _TECHMAP_FAIL_ = 1; - else - // Since negative indices are out of the range of A - // and hence return 'bx, drop the sign bit - \$__XILINX_SHIFTX #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(0), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-1'd1), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y) - ); + if (B_SIGNED) begin + if (B_WIDTH < 4 || A_WIDTH <= 4) + wire _TECHMAP_FAIL_ = 1; + else + // Since negative indices are out of the range of A + // and hence return 'bx, drop the sign bit + \$__XILINX_SHIFTX #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(0), + .A_WIDTH(A_WIDTH), + .B_WIDTH($clog2(A_WIDTH*B_WIDTH)), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y) + ); end else begin if (B_WIDTH < 3 || A_WIDTH <= 4) |