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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-15 16:29:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 4cec21b93e62e9c43a0ab9618c0111ee65e520c1 (patch) | |
| tree | ebb686ef074dc53bd8f471d88f6af469bae340e7 /techlibs | |
| parent | 6c66030dfbcd93024f5f5bb602b9fcc58cb80a88 (diff) | |
| download | yosys-4cec21b93e62e9c43a0ab9618c0111ee65e520c1.tar.gz yosys-4cec21b93e62e9c43a0ab9618c0111ee65e520c1.tar.bz2 yosys-4cec21b93e62e9c43a0ab9618c0111ee65e520c1.zip | |
abc9_ops: -prep_dff_map to error if async flop found
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5143f87da..25df3a865 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -656,7 +656,6 @@ module FDRSE ( Q <= d; endmodule -(* lib_whitebox *) module FDCE ( output reg Q, (* clkbuf_sink *) @@ -699,7 +698,6 @@ module FDCE ( endspecify endmodule -(* lib_whitebox *) module FDCE_1 ( output reg Q, (* clkbuf_sink *) @@ -724,7 +722,6 @@ module FDCE_1 ( endspecify endmodule -(* lib_whitebox *) module FDPE ( output reg Q, (* clkbuf_sink *) @@ -766,7 +763,6 @@ module FDPE ( endspecify endmodule -(* lib_whitebox *) module FDPE_1 ( output reg Q, (* clkbuf_sink *) |