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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-26 13:42:53 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-26 13:42:53 -0700 |
| commit | 44fd3cd149786bc3aaf180af8ec83f790d9cebbe (patch) | |
| tree | 6af18376419c2053cbfef0d986925b1eedb11a91 /techlibs | |
| parent | af15b92c861f11d1f4b5016fed0cb8cb45af9175 (diff) | |
| download | yosys-44fd3cd149786bc3aaf180af8ec83f790d9cebbe.tar.gz yosys-44fd3cd149786bc3aaf180af8ec83f790d9cebbe.tar.bz2 yosys-44fd3cd149786bc3aaf180af8ec83f790d9cebbe.zip | |
Added GP_LFOSC cell
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 54e5a423c..249ea286c 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -63,3 +63,20 @@ module GP_VSS(output OUT); assign OUT = 0; endmodule +module GP_LFOSC(input PWRDN, output reg CLKOUT); + parameter PWRDN_EN = 0; + parameter AUTO_ON = 0; + + initial CLKOUT = 0; + + always begin + if(PWRDN) + clkout = 0; + else begin + //half period of 1730 Hz + #289017; + clkout = ~clkout; + end + end + +endmodule |