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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 14:57:38 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 14:57:38 -0700 |
commit | 3b9b0fcd0630133092b23a18453eb420534b2369 (patch) | |
tree | 66ad94edfbbc13ffc53f605a6e19c12e00c491de /techlibs | |
parent | 64a72ed51e9d21cf5f30e3ff87856c808cf53a29 (diff) | |
download | yosys-3b9b0fcd0630133092b23a18453eb420534b2369.tar.gz yosys-3b9b0fcd0630133092b23a18453eb420534b2369.tar.bz2 yosys-3b9b0fcd0630133092b23a18453eb420534b2369.zip |
Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/ice40/synth_ice40.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 55aa72aa7..284bc90d0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,9 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); + run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " + "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " + "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("opt_expr -fine", " (if -dsp)"); run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); |