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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-05 11:17:40 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-05 11:18:38 +0200 |
| commit | 3b52121d328d45a5d4269fd0e8de9af948c0216e (patch) | |
| tree | 59d61572353b98e449d72f4802c4e7c164f7b5eb /techlibs | |
| parent | ee8ad72fd950e1ee204e5c97155a50b8b1445dec (diff) | |
| download | yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.tar.gz yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.tar.bz2 yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.zip | |
now ignore init attributes on non-register wires in sat command
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions