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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:02:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:02:53 -0700 |
| commit | 2f770b7400f6b12ca13e68496977094f92c13680 (patch) | |
| tree | 81dc1aeb54bf66d2ac1acd66975fc86e71cc4546 /techlibs | |
| parent | a19226c174e31da444b831706adf7fa17e9cb9e4 (diff) | |
| download | yosys-2f770b7400f6b12ca13e68496977094f92c13680.tar.gz yosys-2f770b7400f6b12ca13e68496977094f92c13680.tar.bz2 yosys-2f770b7400f6b12ca13e68496977094f92c13680.zip | |
Use LUT delays for dist RAM delays
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 40b92da0c..8c046cdbc 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -34,12 +34,12 @@ CARRY4 3 1 10 8 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Outputs: DPO SPO RAM64X1D 4 0 15 2 -- - - - - - - 124 124 124 124 124 124 - - -124 124 124 124 124 124 - - - - - - 124 - - +- - - - - - - 642 631 472 407 238 127 - - +642 631 472 407 238 127 - - - - - - - - - # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO RAM128X1D 5 0 17 2 -- - - - - - - - 314 314 314 314 314 314 292 - - -347 347 347 347 347 347 296 - - - - - - - - - - +- - - - - - - - 1009 998 839 774 605 494 450 - - +1047 1036 877 812 643 532 478 - - - - - - - - - - |