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| author | David Shah <dave@ds0.me> | 2019-07-08 21:04:33 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-08 21:04:33 +0100 |
| commit | 22334fea403fb94dc2b6b583b2f681527c21883e (patch) | |
| tree | 7a5afb53626bbe7ca940c984716bd5d19fbee609 /techlibs | |
| parent | 030483ffb909ab38e10d437d09ec922cb0ad2ce8 (diff) | |
| parent | 4f798cda9d1b05d141e16a21b9e357de364021de (diff) | |
| download | yosys-22334fea403fb94dc2b6b583b2f681527c21883e.tar.gz yosys-22334fea403fb94dc2b6b583b2f681527c21883e.tar.bz2 yosys-22334fea403fb94dc2b6b583b2f681527c21883e.zip | |
Merge pull request #1160 from ZirconiumX/cyclone_v
synth_intel: Warn about untested Quartus backend
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 639cba2c2..09c9ba3af 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -48,6 +48,8 @@ struct SynthIntelPass : public ScriptPass { log(" -vqm <file>\n"); log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); + log(" Note that this backend has not been tested and is likely incompatible\n"); + log(" with recent versions of Quartus.\n"); log("\n"); log(" -vpr <file>\n"); log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); @@ -108,6 +110,7 @@ struct SynthIntelPass : public ScriptPass { } if (args[argidx] == "-vqm" && argidx + 1 < args.size()) { vout_file = args[++argidx]; + log_warning("The Quartus backend has not been tested recently and is likely incompatible with modern versions of Quartus.\n"); continue; } if (args[argidx] == "-vpr" && argidx + 1 < args.size()) { |