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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:43:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:43:29 -0700 |
| commit | 1abe93e48d8bb78cd0753d46dfbe1885a1e803eb (patch) | |
| tree | ecaa95a9e3b9c87a528a6939a36053012cbea563 /techlibs | |
| parent | 0f300e75c07dbcf21ab2d6128ef8af9ca6a98892 (diff) | |
| parent | e01bab6c6437f7e3072e10beaec558d3f71c3e9e (diff) | |
| download | yosys-1abe93e48d8bb78cd0753d46dfbe1885a1e803eb.tar.gz yosys-1abe93e48d8bb78cd0753d46dfbe1885a1e803eb.tar.bz2 yosys-1abe93e48d8bb78cd0753d46dfbe1885a1e803eb.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/arith_map.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index eb7947601..17bde0497 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -50,20 +50,21 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH2-1:0] AA = A_buf; wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH2-1:0] BX = B_buf; wire [Y_WIDTH2-1:0] C = {CO, CI}; wire [Y_WIDTH2-1:0] FCO, Y1; genvar i; generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice CCU2C #( - .INIT0(16'b0110011010101010), - .INIT1(16'b0110011010101010), + .INIT0(16'b1001011010101010), + .INIT1(16'b1001011010101010), .INJECT1_0("NO"), .INJECT1_1("NO") ) ccu2c_i ( .CIN(C[i]), - .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), - .A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1), .S0(Y[i]), .S1(Y1[i]), .COUT(FCO[i]) ); |