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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
| commit | 0d7e71f7abd49d1c95f0657993b55bb5f66317a1 (patch) | |
| tree | b2f77c79c6335d9b2b9dde1938f445c48ba00164 /techlibs | |
| parent | 0c83a30f950d766ddd09bb744ee93e2433095b5c (diff) | |
| parent | ef4a28e112be10d3d62395f68e53e8b7e42dbf68 (diff) | |
| download | yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.gz yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.bz2 yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2c4db1ac6..d0abd3b34 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,6 +1305,14 @@ endmodule // -------------------------------------------------------- +module \$cover (A, EN); + +input A, EN; + +endmodule + +// -------------------------------------------------------- + module \$initstate (Y); output reg Y = 1; |