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| author | Clifford Wolf <clifford@clifford.at> | 2016-02-07 11:19:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-02-07 11:19:48 +0100 |
| commit | 0ccfb88728c5bdf167b1d672034ca5cf360dedb1 (patch) | |
| tree | 13f2f434d9d7ae720067df7d400f98b40df64b1b /techlibs | |
| parent | e7bec9bbb8ca9dd58c8a2fbf7ea0d2010fc40f5f (diff) | |
| download | yosys-0ccfb88728c5bdf167b1d672034ca5cf360dedb1.tar.gz yosys-0ccfb88728c5bdf167b1d672034ca5cf360dedb1.tar.bz2 yosys-0ccfb88728c5bdf167b1d672034ca5cf360dedb1.zip | |
Work around DDR dout sim glitches in ice40 SB_IO sim model
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f23218c00..7778b5519 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -47,11 +47,17 @@ module SB_IO ( din_1 = din_q_1; end + // work around simulation glitches on dout in DDR mode + reg outclk_delayed_1; + reg outclk_delayed_2; + always @* outclk_delayed_1 <= OUTPUT_CLK; + always @* outclk_delayed_2 <= outclk_delayed_1; + always @* begin if (PIN_TYPE[3]) dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0; else - dout = (OUTPUT_CLK ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1; + dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1; end assign D_IN_0 = din_0, D_IN_1 = din_1; |