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| author | Clifford Wolf <clifford@clifford.at> | 2017-05-17 09:08:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-05-17 09:08:29 +0200 |
| commit | 05cdd58c8dc73968992681d0ee1cbfa89880b94f (patch) | |
| tree | 426fabb50c83d45f1194bd94125d4701242e920f /techlibs | |
| parent | 9f4fbc5e74747c8973da3a2fd42d2ef40dbe1fa5 (diff) | |
| download | yosys-05cdd58c8dc73968992681d0ee1cbfa89880b94f.tar.gz yosys-05cdd58c8dc73968992681d0ee1cbfa89880b94f.tar.bz2 yosys-05cdd58c8dc73968992681d0ee1cbfa89880b94f.zip | |
Add $_ANDNOT_ and $_ORNOT_ gates
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simcells.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index e770c5453..937512e7c 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -175,6 +175,44 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- +//- $_ANDNOT_ (A, B, Y) +//- +//- A 2-input AND-NOT gate. +//- +//- Truth table: A B | Y +//- -----+--- +//- 0 0 | 0 +//- 0 1 | 0 +//- 1 0 | 1 +//- 1 1 | 0 +//- +module \$_ANDNOT_ (A, B, Y); +input A, B; +output Y; +assign Y = A & (~B); +endmodule + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_ORNOT_ (A, B, Y) +//- +//- A 2-input OR-NOT gate. +//- +//- Truth table: A B | Y +//- -----+--- +//- 0 0 | 1 +//- 0 1 | 0 +//- 1 0 | 1 +//- 1 1 | 1 +//- +module \$_ORNOT_ (A, B, Y); +input A, B; +output Y; +assign Y = A | (~B); +endmodule + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- //- $_MUX_ (A, B, S, Y) //- //- A 2-input MUX gate. |